Physical Implementation (PI) Engineer

LOCATION: Ho Chi Minh City, Vietnam
REPORT TO: Department Head (Vietnam) / Korea HQ

About the Client
Our client, a global semiconductor design company and strategic partner of a leading foundry, is expanding its Physical Implementation team in Vietnam to work on advanced nodes (2nm–14nm).

Key Requirements
Experience
- Senior/Staff level: 5+ years of experience in ASIC/SoC implementation or logical signoff.
- Lead level: 8+ years of experience, with at least 2+ years in a technical lead or mentoring role.
- Experience handling RTL-to-gate implementation and signoff activities for advanced ASIC/SoC designs.
- Experience supporting block-level or subsystem-level timing and logical closure.
- Experience with ECO implementation and incremental signoff flows.
- Experience collaborating with RTL, DFT, Physical Design, Verification, and Foundry teams.

Technical Skills
- Strong hands-on experience with Synopsys tools: Design Compiler NXT, Fusion Compiler, PrimeTime, Formality, VC LP, SpyGlass (Cadence experience is a plus).
- Programming / Scripting: Tcl scripting, Shell scripting, Python programming preferred.
- Strong understanding of CMOS digital design, Timing closure methodology, ASIC implementation flow, Formal verification concepts, Low-power design methodology, SDC constraints, MMMC flows, UPF / CPF, ECO flow, OCV / AOCV / POCV methodologies, Crosstalk and signal integrity (SI) analysis, DFT-aware implementation, Low-power signoff methodology.
- Experience with advanced technology nodes: 14nm, 7nm, 4nm, 2nm.
- Experience with Hierarchical SoC integration, Large CPU/GPU/NPU subsystems, Automotive or high-reliability design flows.
- Knowledge of: CDC/RDC verification, Physical-aware synthesis, MMMC timing optimization, ECO automation frameworks.
- Strong analytical, debugging, and problem-solving skills.

Soft Skills
- Fluent English for both written and verbal communications. Knowing Korean is a plus.
- Collaboration with other teams to resolve problems.
- Self-motivated with the ability to manage multiple priorities.

Key Responsibilities
Logic Synthesis
- Perform RTL synthesis using Synopsys Design Compiler or Fusion Compiler.
- Develop and maintain synthesis scripts, constraints, and automation flows.
- Analyze and optimize timing, area, and power.
- Handle clock gating, multi-voltage designs, UPF-based implementation, hierarchical and top-level synthesis.
- Debug synthesis issues, including unconstrained paths, timing loops, high fanout, constant propagation, mapping inconsistencies, etc.

Static Timing Analysis (STA)
- Perform pre-layout and post-layout STA using Synopsys PrimeTime.
- Create and validate SDC constraints, including clock definitions, clock relationships, timing exceptions.
- Analyze setup/hold violations, CDC-related timing issues, crosstalk impacts, OCV/AOCV/POCV effects, IR-drop-related timing degradation, etc.
- Support MMMC timing closure across functional and test modes.
- Generate signoff timing reports and debug timing regressions.

Logic Equivalence Check (LEC)
- Perform RTL-to-netlist and netlist-to-netlist equivalence checking using Synopsys Formality.
- Debug equivalence failures caused by retiming, clock gating insertion, scan insertion, synthesis optimizations, ECO modifications, etc.
- Develop automated LEC regression and reporting flows.
- Ensure clean signoff equivalence before tapeout.

Low Power Verification (CLP)
- Verify low-power architecture and UPF intent using Synopsys VC LP.
- Validate isolation strategy, retention logic, level shifters, power state transitions, always-on cell placement and connectivity, etc.
- Debug UPF inconsistencies and low-power structural violations.
- Collaborate with architecture and RTL teams to ensure power intent correctness.

Logic Design Rule Check (LDRC)
- Run logic structural checks using Synopsys SpyGlass or equivalent methodology.
- Analyze and resolve combinational loops, multiple-driver conditions, X-propagation risks, reset/clock domain structural issues, lint violations, synthesis rule violations, etc.
- Drive RTL quality improvement before implementation.

Additional Responsibilities
- Support ECO implementation and incremental signoff.
- Collaborate with RTL design teams, Physical design teams, DFT engineers, Verification engineers, Foundry support teams.
- Improve flow robustness and runtime through Tcl/Python automation.
- Participate in methodology development and signoff reviews.
- Mentor junior engineers.

Education
Bachelor's degree or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related engineering discipline.