STAFF / SENIOR STAFF – DESIGN FOR TEST (DFT) ENGINEER

Key Requirements

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• At least 5 years of experience in Design-for-Test (DFT) implementation for digital IC design.
• Strong knowledge of DFT methodologies, including Scan, MBIST, and Boundary Scan.
• Hands-on experience with DFT implementation, verification, pattern generation, simulation, and validation.
• Good understanding of Static Timing Analysis (STA) and timing constraints related to DFT implementation.
• Experience supporting DFT verification, debug, and design quality improvement.
• Familiarity with industry-standard EDA tools for DFT implementation and verification.
• Strong analytical, debugging, and problem-solving skills.
• Good communication skills and the ability to work effectively in a collaborative engineering environment.
• Experience with advanced semiconductor technologies is an advantage.

Key Responsibilities

• Develop and implement DFT solutions for complex digital IC designs.
• Execute DFT implementation activities throughout the chip development lifecycle.
• Collaborate with cross-functional engineering teams to ensure successful DFT integration.
• Perform DFT verification, simulation, debugging, and quality checks.
• Support design optimization and continuous improvement of DFT methodologies and engineering processes.
• Investigate and resolve technical issues related to DFT implementation.
• Contribute to technical discussions and share best practices within the engineering team.
• Provide guidance and technical support to junior engineers when required.

Education

• Bachelor's degree or above in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

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