DFT Engineer

DFT Engineer / Lead Engineer (Design for Test) – IC Design Services / Outsourcing Company

Job Summary

We are looking for a DFT Engineer / Lead Engineer to develop and implement Design-for-Test (DFT) solutions for complex ASIC and SoC projects. The role will work closely with RTL Design, Verification, Physical Design, and customer teams to ensure high test coverage, manufacturability, and production readiness for semiconductor products.

Key Responsibilities

• Define and implement DFT architecture for ASIC and SoC designs.
• Develop and integrate Scan, MBIST, LBIST, JTAG, Boundary Scan, and ATPG methodologies.
• Perform DFT insertion, verification, and test coverage analysis.
• Generate and debug ATPG patterns for manufacturing tests.
• Collaborate with Design, Verification, Physical Design, and Product Engineering teams throughout the chip development cycle.
• Support silicon bring-up, failure analysis, and production ramp activities.
• Prepare technical documentation and customer deliverables.
• Work directly with global customers and offshore engineering teams.

For Lead Engineer:

• Lead DFT development for multiple projects or large SoC programs.
• Drive DFT methodology improvements and best practices.
• Review technical solutions and mentor junior engineers.
• Coordinate customer discussions and project planning.

Requirements

Engineer

• Bachelor's or Master's Degree in Electronics, Semiconductor, Computer Engineering, or related disciplines.
• 3+ years of experience in DFT engineering.
• Hands-on experience with Scan, ATPG, MBIST, and JTAG implementation.
• Knowledge of ASIC/SoC design flow and semiconductor manufacturing.

Lead Engineer

• 7+ years of DFT experience with technical leadership responsibilities.
• Proven experience leading DFT activities for advanced-node ASIC or SoC projects.
• Strong customer-facing and project coordination skills.

Technical Skills

• DFT methodologies: Scan, Compression, MBIST, LBIST, JTAG, Boundary Scan.
• ATPG and DFT tools such as Synopsys TestMAX / DFT Compiler, Cadence Modus, or Siemens Tessent.
• Verification tools and scripting languages (Perl, Tcl, Python, Shell).
• Experience with RTL design and verification environments is an advantage.
• Understanding of semiconductor test, yield improvement, and silicon debug processes.

Preferred Background

• IC Design Services, ASIC Design, or Semiconductor Design Houses.
• Experience working in outsourcing/service companies supporting global semiconductor customers.
• Exposure to projects in AI, Automotive, Consumer Electronics, Networking, or High-Performance Computing.

Language

• Good English communication skills for direct interaction with international customers and engineering teams.

 

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